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Financement de l’UE (3 123 966 €) : Matrice photonique sur silicium à grande échelle pour les centres de données à faible consommation d’énergie et à faible coût Hor01/12/2015 Programme de recherche et d'innovation de l'UE « Horizon »
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Matrice photonique sur silicium à grande échelle pour les centres de données à faible consommation d’énergie et à faible coût
Cloud storage and computing, big data analytics and social media are driving the need for higher bandwidth communications in data centres (DCs). Concurrently, disaggregation and virtualization trends in the DC are forcing the traffic to be between servers and storage elements in the east-west direction. These changes require massive switching capabilities from the discrete switch elements. However, the technology is rapidly reaching a limit. The result is a multi-layered DC topology with high power consumption and long latency. The L3MATRIX project provides novel technological innovations in the fields of silicon photonics (SiP) and 3D device integration. The project will develop a novel SiP matrix with a scale larger than any similar device with more than 100 modulators on a single chip and will integrate embedded laser sources with a logic chip thus breaking the limitations on the bandwidth-distance product. Use of embedded laser sources and integration with a full logic CMOS chip are innovative steps that will have a profound effect on the European market as these technologies will make a noticeable change in the power consumption, performance and cost of DCs. A novel approach will be used with embedded III-V sources on the SOI substrate which will eliminate the need to use an external light source for the modulators. L3MATRIX provides a new method of building switching elements that are both high radix and have an extended bandwidth of 25 Gb/s in single mode fibres and waveguides with low latency. The power consumption of DC networks built with these devices is 10-fold lower compared to the conventional technology. The outcome of this approach is that large networks, in the Pb/s scale can be built as a single stage, non-blocking network. The single mode nature of the SiP chip allows scaling the network to the 2000 m range required in modern DCs.
| AMS-Osram AG | 602 205 € |
| Aristotelio Panepistimio Thessalonikis | 482 000 € |
| BRIGHT PHOTONICS B.V. | 150 875 € |
| COMPAS ELECTRO-OPTICAL SYSTEMS Ltd. | 0,00 € |
| DUSTPHOTONICS Ltd. | 525 813 € |
| FRAUNHOFER GESELLSCHAFT ZUR FORDERUNG DER ANGEWANDTEN FORSCHUNG e. V. | 595 175 € |
| IBM RESEARCH GmbH | 0,00 € |
| Universitat Politecnica de Valencia | 444 561 € |
| University College London | 323 338 € |
https://cordis.europa.eu/project/id/688544
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