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Financement de l’UE (3 745 608 €) : Calcul à ondes de spin pour une électronique hybride basse consommation à l’échelle ultime Hor 01/05/2018 Programme de recherche et d'innovation de l'UE « Horizon »
Vue d’ensemble
Texte
Calcul à ondes de spin pour une électronique hybride basse consommation à l’échelle ultime
The future miniaturisation of electronic circuits following Moore’s law will require the introduction of increasingly disruptive technologies to limit power consumption and optimise performance per circuit area. CHIRON envisions spin wave computing to complement and eventually replace CMOS in future microelectronics. Spin wave computing is a paradigm-shifting technology that uses the interference of spin waves for computation. Spin wave computing has the potential for significant power and area reduction per computing throughput while reducing cost by alleviating lithography requirements. As a first step towards the vision of a full spin wave computer, CHIRON envisions hybrid spin wave–CMOS circuits that can be readily integrated alongside CMOS. CHIRON targets a proof of principle of the essential elements for spin wave computing by an interdisciplinary approach joining partners with expertise in material science, physics, nano-manufacturing, electrical engineering, device simulation, and circuit design. CHIRON will fabricate basic logic gates, such as inverters and majority gates, demonstrate their operation, and assess their performance. As transducers between the CMOS and spin wave domains in hybrid circuits, CHIRON will develop magnetoelectric and multiferroic nanoresonators, based on nanoscale bulk acoustic resonators, which bear promise for high energy efficiency and large output signal. The targeted lateral scale (100 nm) and resonance frequency (>10 GHz) bring such resonators to the frontier of nano-electromechanical systems (NEMS). This technological proof of principle is complemented by the design of digital hybrid spin wave–CMOS circuits that show the advantages of spin wave computing and can be integrated into a CMOS environment. Based on calibrated compact device models, the performance of these circuits in terms of power, area, and throughput will be benchmarked against CMOS to demonstrate their viability.
| Centre National de la Recherche Scientifique CNRS | 554 315 € |
| Idryma Technologias Kai Erevnas | 283 750 € |
| Institutul National de Cercetaredezvoltare Pentru Microtehnologie | 220 438 € |
| Interuniversitair Micro-Electronica Centrum | 675 726 € |
| Rheinland-Pfalzische Technische Universitat | 389 825 € |
| Solmates B.V. | 512 875 € |
| Technische Universiteit Delft | 413 324 € |
| Thales | 254 330 € |
| Universite Paris-Saclay | 441 025 € |
https://cordis.europa.eu/project/id/801055
Cette annonce se réfère à une date antérieure et ne reflète pas nécessairement l’état actuel.